80960CA-25 Datasheet, PDF (38/62 Pages) Intel Corporation – SPECIAL ENVIRONMENT 80960CA-25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

SPECIAL ENVIRONMENT 80960CA-25 -16
NOTE
Case 1 and Case 2 show two possible polarities of PCLK2 1
Figure 21 Clock Synchronization in the 2-x Clock Mode
271327 – 21
271327 – 22
NOTE
In 1x clock mode the RESET pin is actually sampled on the falling edge of 2xCLK 2xCLK is an internal signal generated
by the PLL and is not available on an external pin Therefore RESET is specified relative to the rising edge of CLKIN
The RESET pin is sampled when PCLK is high
Figure 22 Clock Synchronization in the 1-x Clock Mode
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