80960CA-25 Datasheet, PDF (4/62 Pages) Intel Corporation – SPECIAL ENVIRONMENT 80960CA-25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

CONTENTS
LIST OF FIGURES (Continued)
Figure 38 Using External READY
Figure 39 Terminating a Burst with BTERM
Figure 40 BOFF Functional Timing
Figure 41 HOLD Functional Timing
Figure 42 DREQ and DACK Functional Timing
Figure 43 EOP Functional Timing
Figure 44 Terminal Count Functional Timing
Figure 45 FAIL Functional Timing
Figure 46 A Summary of Aligned and Unaligned Transfers for Little Endian Regions
Figure 47 A Summary of Aligned and Unaligned Transfers for Little Endian Regions
(Continued)
Figure 48 Idle Bus Operation
LIST OF TABLES
Table 1 80960CA Instruction Set
Table 2 Pin Description Nomenclature
Table 3 80960CA Pin Description External Bus Signals
Table 4 80960CA Pin Description Processor Control Signals
Table 5 80960CA Pin Description DMA and Interrupt Unit Control Signals
Table 6 80960CA PGA Pinout In Signal Order
Table 7 80960CA PGA Pinout In Pin Order
Table 8 Maximum T_A at Various Airflows in C
Table 9 80960CA PGA Package Thermal Characteristics
Table 10 Die Stepping Cross Reference
Table 11 Operating Conditions (80960CA-25 -16)
Table 12 DC Characteristics
Table 13 80960CA AC Characteristics (25 MHz)
Table 14 80960CA AC Characteristics (16 MHz)
Table 15 Reset Conditions
Table 16 Hold Acknowledge and Backoff Conditions
PAGE
54
55
56
57
58
58
59
59
60
61
62
7
8
9
12
14
15
16
19
20
21
22
23
24
26
34
34
4