80960CA-25 Datasheet, PDF (14/62 Pages) Intel Corporation – SPECIAL ENVIRONMENT 80960CA-25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

SPECIAL ENVIRONMENT 80960CA-25 -16
Table 5 80960CA Pin Description DMA and Interrupt Unit Control Signals
Name
DREQ3 0
DACK3 0
EOP TC3 0
XINT7 0
NMI
Type
I
A(L)
H(Z)
R(Z)
O
S
H(1)
R(1)
IO
A(L)
H(Z Q)
R(Z)
I
A(E L)
H(Z)
R(Z)
I
A(E)
H(Z)
R(Z)
Description
DMA REQUEST causes a DMA transfer to be requested Each of the four
signals requests a transfer on a single channel DREQ0 requests channel 0
DREQ1 requests channel 1 etc When two or more channels are requested
simultaneously the channel with the highest priority is serviced first The
channel priority mode is programmable
DMA ACKNOWLEDGE indicates that a DMA transfer is being executed
Each of the four signals acknowledges a transfer for a single channel DACK0
acknowledges channel 0 DACK1 acknowledges channel 1 etc DACK3 0 are
asserted when the requesting device of a DMA is accessed
END OF PROCESS TERMINAL COUNT can be programmed as either an
input (EOP3 0) or as an output (TC3 0) but not both Each pin is individually
programmable When programmed as an input EOPx causes the termination
of a current DMA transfer for the channel corresponding to the EOPx pin
EOP0 corresponds to channel 0 EOP1 corresponds to channel 1 etc When
a channel is configured for source and destination chaining the EOP pin for
that channel causes termination of only the current buffer transferred and
causes the next buffer to be transferred EOP3 0 are asynchronous inputs
When programmed as an output the channel’s TCx pin indicates that the
channel byte count has reached 0 and a DMA has terminated TCx is driven
with the same timing as DACKx during the last DMA transfer for a buffer If the
last bus request is executed as multiple bus accesses TCx will stay asserted
for the entire bus request
EXTERNAL INTERRUPT PINS cause interrupts to be requested These pins
can be configured in three modes
Dedicated Mode
each pin is a dedicated external interrupt source
Dedicated inputs can be individually programmed to
be level (low) or edge (falling) activated
Expanded Mode
the eight pins act together as an 8-bit vectored
interrupt source The interrupt pins in this mode are
level activated Since the interrupt pins are active low
the vector number requested is the one’s
complement of the positive logic value place on the
port This eliminates glue logic to interface to
combinational priority encoders which output
negative logic
Mixed Mode
XINT7 5 are dedicated sources and XINT4 0 act as
the five most significant bits of an expanded mode
vector The least significant bits are set to 010
internally
NON-MASKABLE INTERRUPT causes a non-maskable interrupt event to
occur NMI is the highest priority interrupt recognized NMI is an edge (falling)
activated source
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