80960CA-25 Datasheet, PDF (8/62 Pages) Intel Corporation – SPECIAL ENVIRONMENT 80960CA-25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

SPECIAL ENVIRONMENT 80960CA-25 -16
3 0 PACKAGE INFORMATION
3 1 Package Introduction
This section describes the pins pinouts and thermal
characteristics for the 80960CA in the 168-pin Ce-
ramic Pin Grid Array (PGA) package For complete
package specifications and information see the
Packaging Handbook (Order No 240800)
3 2 Pin Descriptions
The 80960CA pins are described in this section Ta-
ble 2 presents the legend for interpreting the pin de-
scriptions in the following tables Pins associated
with the 32-bit demultiplexed processor bus are de-
scribed in Table 3 Pins associated with basic proc-
essor configuration and control are described in Ta-
ble 4 Pins associated with the 80960CA DMA Con-
troller and Interrupt Unit are described in Table 5
All pins float while the processor is in the ONCE
mode
Table 2 Pin Description Nomenclature
Symbol
Description
I
Input only pin
O Output only pin
I O Pin can be either an input or output
Pins ‘‘must be’’ connected as described
S( )
Synchronous Inputs must meet setup
and hold times relative to PCLK2 1 for
proper operation All outputs are
synchronous to PCLK2 1
S(E) Edge sensitive input
S(L) Level sensitive input
A( )
Asynchronous Inputs may be
asynchronous to PCLK2 1
A(E) Edge sensitive input
A(L) Level sensitive input
H( )
While the processor’s bus is in the Hold
Acknowledge or Bus Backoff state the
pin
H(1) is driven to V_CC
H(0) is driven to V_SS
H(Z) floats
H(Q) continues to be a valid input
R( )
While the processor’s RESET pin is low
the pin
R(1) is driven to V_CC
R(0) is driven to V_SS
R(Z) floats
R(Q) continues to be a valid output
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