80960CA-25 Datasheet, PDF (3/62 Pages) Intel Corporation – SPECIAL ENVIRONMENT 80960CA-25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

CONTENTS
LIST OF FIGURES
Figure 1 80960CA Block Diagram
Figure 2 80960CA PGA Pinout View from Top (Pins Facing Down)
Figure 3 80960CA PGA Pinout View from Bottom (Pins Facing Up)
Figure 4 Measuring 80960CA PGA Case Temperature
Figure 5 Register g0
Figure 6 AC Test Load
Figure 7 Input and Output Clocks Waveform
Figure 8 CLKIN Waveform
Figure 9 Output Delay and Float Waveform
Figure 10 Input Setup and Hold Waveform
Figure 11 NMI XINT7 0 Input Setup and Hold Waveform
Figure 12 Hold Acknowledge Timings
Figure 13 Bus Backoff (BOFF) Timings
Figure 14 Relative Timings Waveforms
Figure 15 Output Delay or Hold vs Load Capacitance
Figure 16 Rise and Fall Time Derating at Highest Operating Temperature
and Minimum V_CC
Figure 17 I_CC vs Frequency and Temperature
Figure 18 Cold Reset Waveform
Figure 19 Warm Reset Waveform
Figure 20 Entering the ONCE State
Figure 21 Clock Synchronization in the 2-x Clock Mode
Figure 22 Clock Synchronization in the 1-x Clock Mode
Figure 23 Non-Burst Non-Pipelined Requests without Wait States
Figure 24 Non-Burst Non-Pipelined Read Request with Wait States
Figure 25 Non-Burst Non-Pipelined Write Request with Wait States
Figure 26 Burst Non-Pipelined Read Request without Wait States 32-Bit Bus
Figure 27 Burst Non-Pipelined Read Request with Wait States 32-Bit Bus
Figure 28 Burst Non-Pipelined Write Request without Wait States 32-Bit Bus
Figure 29 Burst Non-Pipelined Write Request with Wait States 32-Bit Bus
Figure 30 Burst Non-Pipelined Read Request with Wait States 16-Bit Bus
Figure 31 Burst Non-Pipelined Read Request with Wait States 8-Bit Bus
Figure 32 Non-Burst Pipelined Read Request without Wait States 32-Bit Bus
Figure 33 Non-Burst Pipelined Read Request with Wait States 32-Bit Bus
Figure 34 Burst Pipelined Read Request without Wait States 32-Bit Bus
Figure 35 Burst Pipelined Read Request with Wait States 32-Bit Bus
Figure 36 Burst Pipelined Read Request with Wait States 16-Bit Bus
Figure 37 Burst Pipelined Read Request with Wait States 8-Bit Bus
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