80960CA-25 Datasheet, PDF (5/62 Pages) Intel Corporation – SPECIAL ENVIRONMENT 80960CA-25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

SPECIAL ENVIRONMENT 80960CA-25 -16
1 0 PURPOSE
This document provides electrical characteristics for
the 25 and 16 MHz versions of the 80960CA For a
detailed description of any 80960CA functional
topic other than parametric performance consult
the 80960CA Product Overview (Order No 270669)
or the i960 CA Microprocessor User’s Manual (Or-
der No 270710) To obtain data sheet updates and
errata please call Intel’s FaxBACK data-on-de-
mand system (1-800-628-2283 or 916-356-3105)
Other information can be obtained from Intel’s tech-
nical BBS (916-356-3600)
2 0 80960CA OVERVIEW
The 80960CA is the second-generation member of
the 80960 family of embedded processors The
80960CA is object code compatible with the 32-bit
80960 Core Architecture while including Special
Function Register extensions to control on-chip pe-
ripherals and instruction set extensions to shift
64-bit operands and configure on-chip hardware
Multiple 128-bit internal buses on-chip instruction
caching and a sophisticated instruction scheduler al-
low the processor to sustain execution of two in-
structions every clock and peak at execution of
three instructions per clock
A 32-bit demultiplexed and pipelined burst bus pro-
vides a 132 Mbyte s bandwidth to a system’s high-
speed external memory sub-system In addition the
80960CA’s on-chip caching of instructions proce-
dure context and critical program data substantially
decouple system performance from the wait states
associated with accesses to the system’s slower
cost sensitive main memory subsystem
The 80960CA bus controller integrates full wait state
and bus width control for highest system perform-
ance with minimal system design complexity Un-
aligned access and Big Endian byte order support
reduces the cost of porting existing applications to
the 80960CA
The processor also integrates four complete data-
chaining DMA channels and a high-speed interrupt
controller on-chip DMA channels perform single-
cycle or two-cycle transfers data packing and un-
packing and data chaining Block transfers in addi-
tion to source or destination synchronized trans-
fers are provided
The interrupt controller provides full programmability
of 248 interrupt sources into 32 priority levels with a
typical interrupt task switch (‘‘latency’’) time of
750 ns
Figure 1 80960CA Block Diagram
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