80960CA-25 Datasheet, PDF (24/62 Pages) Intel Corporation – SPECIAL ENVIRONMENT 80960CA-25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

SPECIAL ENVIRONMENT 80960CA-25 -16
4 5 AC Specifications
Table 13 80960CA AC Characteristics (25 MHz)
(80960CA-25 only under conditions described in Section 4 2 Operating Conditions and Section 4 5 1
AC Test Conditions )
Symbol
Parameter
Input Clock (1 9)
T_F
CLKIN Frequency
T_C
CLKIN Period
T_CS
CLKIN Period Stability
T_CH
CLKIN High Time
T_CL
CLKIN Low Time
T_CR
CLKIN Rise Time
T_CF
CLKIN Fall Time
Output Clocks (1 8)
In 1-x Mode (f_CLK1x)
In 2-x Mode (f_CLK2x)
In 1-x Mode (f_CLK1x)
In 1-x Mode (f_CLK1x)
In 2-x Mode (f_CLK2x)
In 1-x Mode (f_CLK1x)
In 2-x Mode (f_CLK2x)
T_CP
CLKIN to PCLK2 1 Delay
T
PCLK2 1 Period
T_PH
PCLK2 1 High Time
T_PL
PCLK2 1 Low Time
T_PR
PCLK2 1 Rise Time
T_PF
PCLK2 1 Fall Time
Synchronous Outputs (8)
In 1-x Mode (f_CLK1x)
In 2-x Mode (f_CLK2x)
In 1-x Mode (f_CLK1x)
In 2-x Mode (f_CLK2x)
T_OH
T_OV
Output Valid Delay Output Hold
T_OH1 T_OV1
T_OH2 T_OV2
T_OH3 T_OV3
T_OH4 T_OV4
T_OH5 T_OV5
T_OH6 T_OV6
T_OH7 T_OV7
T_OH8 T_OV8
T_OH9 T_OV9
T_OH10 T_OV10
T_OH11 T_OV11
T_OH12 T_OV12
T_OH13 T_OV13
T_OH14 T_OV14
T_OF
Output Float for all ouputs
Synchronous Inputs (1 9 10)
A31 2
BE3 0
ADS
WR
D C SUP DMA
BLAST WAIT
DEN
HOLDA BREQ
LOCK
DACK3 0
D31 0
DT R
FAIL
EOP3 0 TC3 0
T_IS
Input Setup
T_IS1
T_IS2
T_IS3
T_IS4
T_IH
Input Hold
T_IH1
T_IH2
T_IH3
T_IH4
D31 0
BOFF
BTERM READY
HOLD
D31 0
BOFF
BTERM READY
HOLD
Min
Max
0
50
40
125
20
%
g0 1%
8
62 5
8
%
8
62 5
8
%
0
6
0
6
b2
2
2
25
T_C
2T_C
(T 2) b 3
T2
(T 2) b 3
T2
1
4
1
4
3
3
6
3
4
5
3
4
4
4
3
T 2a3
2
3
3
16
18
20
20
18
18
18
18
18
20
18
T 2 a 16
16
20
22
5
19
9
9
5
7
2
5
Units
MHz
ns
ns
D
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes
(11)
(12)
(11)
(11)
(3 12)
(3)
(12)
(3)
(12)
(12)
(3)
(3)
(6 10)
(6 10)
(6)
24