80960CA-25 Datasheet, PDF (58/62 Pages) Intel Corporation – SPECIAL ENVIRONMENT 80960CA-25, -16 32-BIT HIGH-PERFORMANCE EMBEDDED PROCESSOR

SPECIAL ENVIRONMENT 80960CA-25 -16
271327 – 42
NOTES
1 Case 1 DREQ must deassert before DACK deasserts Applications are Fly-By and some packing and unpacking
modes in which loads are followed by loads or stores are followed by stores
2 Case 2 DREQ must be deasserted by the second clock (rising edge) after DACK is driven high Applications are non
Fly-By transfers and adjacent load-stores or store-loads
3 DACKx is asserted for the duration of a DMA bus request The request may consist of multiple bus accesses (defined
by ADS and BLAST Refer to i960 CA Microprocessor User’s Manual for ‘‘access’’ ‘‘request’’ definitions
Figure 42 DREQ and DACK Functional Timing
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NOTE
EOP has the same AC Timing Requirements as DREQ to prevent unwanted DMA requests EOP is NOT edge triggered
EOP must be held for a minimum of 2 clock cycles then deasserted within 15 clock cycles
Figure 43 EOP Functional Timing
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