80960JD Datasheet, PDF (7/61 Pages) Intel Corporation – EMBEDDED 32-BIT MICROPROCESSOR

A
80960JD
Users may configure the 80960JD’s bus controller to
match an application’s fundamental memory organi-
zation. Physical bus width is register-programmed for
up to eight regions. Byte ordering and data caching
are programmed through a group of logical memory
templates and a defaults register.
The BCU’s features include:
• Multiplexed external bus to minimize pin count
• 32-, 16- and 8-bit bus widths to simplify I/O
interfaces
• External ready control for address-to-data, data-to-
data and data-to-next-address wait state types
• Support for big or little endian byte ordering to
facilitate the porting of existing program code
• Unaligned bus accesses performed transparently
• Three-deep load/store queue to decouple the bus
from the core
Upon reset, the 80960JD conducts an internal self
test. Then, before executing its first instruction, it
performs an external bus confidence test by
performing a checksum on the first words of the
initialization boot record (IBR).
The user may examine the contents of the caches at
any time by executing special cache control instruc-
tions.
2.3 Timer Unit
The timer unit (TU) contains two independent 32-bit
timers which are capable of counting at several clock
rates and generating interrupts. Each is programmed
by use of the TU registers. These memory-mapped
registers are addressable on 32-bit boundaries. The
timers have a single-shot mode and auto-reload
capabilities for continuous operation. Each timer has
an independent interrupt request to the 80960JD’s
interrupt controller. The TU can generate a fault
when unauthorized writes from user mode are
detected. Clock prescaling is supported.
2.4 Priority Interrupt Controller
A programmable interrupt controller manages up to
240 external sources through an 8-bit external
interrupt port. Alternatively, the interrupt inputs may
be configured for individual edge- or level-triggered
PRELIMINARY
inputs. The interrupt unit (IU) also accepts interrupts
from the two on-chip timer channels and a single
Non-Maskable Interrupt (NMI) pin. Interrupts are
serviced according to their priority levels relative to
the current process priority.
Low interrupt latency is critical to many embedded
applications. As part of its highly flexible interrupt
mechanism, the 80960JD exploits several
techniques to minimize latency:
• Interrupt vectors and interrupt handler routines can
be reserved on-chip
• Register frames for high-priority interrupt handlers
can be cached on-chip
• The interrupt stack can be placed in cacheable
memory space
• Interrupt microcode executes at twice the bus
frequency
2.5 Instruction Set Summary
The 80960Jx adds several new instructions to the
i960 core architecture. The new instructions are:
• Conditional Move
• Conditional Add
• Conditional Subtract
• Byte Swap
• Halt
• Cache Control
• Interrupt Control
Table 1 identifies the instructions that the 80960Jx
supports. Refer to i960^® Jx Microprocessor User’s
Guide (272483) for a detailed description of each
instruction.
2.6 Faults and Debugging
The 80960Jx employs a comprehensive fault model.
The processor responds to faults by making implicit
calls to a fault handling routine. Specific information
collected for each fault allows the fault handler to
diagnose exceptions and recover appropriately.
The processor also has built-in debug capabilities. In
software, the 80960Jx may be configured to detect
as many as seven different trace event types. Alter-
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