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80960JD Datasheet, PDF (36/61 Pages) Intel Corporation – EMBEDDED 32-BIT MICROPROCESSOR
80960JD
A
Table 18. 80960JD AC Characteristics (33 MHz) (Sheet 2 of 2)
Symbol
Parameter
Min
Max
Units
Notes
BOUNDARY SCAN TEST SIGNAL TIMINGS
TBSF
TCK Frequency
TBSCH
TCK High Time
15
TBSCL
TCK Low Time
15
TBSCR
TCK Rise Time
TBSCF
TCK Fall Time
TBSIS1
Input Setup to TCK — TDI, TMS
4
TBSIH1
Input Hold from TCK — TDI, TMS
6
TBSOV1 TDO Valid Delay
3
TBSOF1 TDO Float Delay
3
TBSOV2 All Outputs (Non-Test) Valid Delay
3
TBSOF2 All Outputs (Non-Test) Float Delay
3
TBSIS2
Input Setup to TCK — All Inputs
4
(Non-Test)
0.5TF
5
5
30
30
30
30
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Measured at 1.5 V (1)
Measured at 1.5 V (1)
0.8 V to 2.0 V (1)
2.0 V to 0.8 V (1)
(1, 10)
(1, 10)
(1, 10)
(1, 10)
TBSIH2
Input Hold from TCK — All Inputs
6
ns
(Non-Test)
NOTES:
1. Not tested.
2. To ensure a 1:1 relationship between the amplitude of the input jitter and the internal clock, the jitter
frequency spectrum should not have any power peaking between 500 KHz and 1/3 of the CLKIN
frequency.
3. Inactive ALE/ALE refers to the falling edge of ALE and the rising edge of ALE. For inactive ALE/ALE
timings, refer to Relative Output Timings in this table.
4. A float condition occurs when the output current becomes less than ILO. Float delay is not tested, but is
designed to be no longer than the valid delay.
5. AD31:0 are synchronous inputs. Setup and hold times must be met for proper processor operation. NMI
and XINT7:0 may be synchronous or asynchronous. Meeting setup and hold time guarantees recog-
nition at a particular clock edge. For asynchronous operation, NMI and XINT7:0 must be asserted for a
minimum of two CLKIN periods to guarantee recognition.
6. RDYRCV and HOLD are synchronous inputs. Setup and hold times must be met for proper processor
operation.
7. RESET may be synchronous or asynchronous. Meeting setup and hold time guarantees recognition at
a particular clock edge.
8. ONCE and STEST must be stable at the rising edge of RESET for proper operation.
9. Guaranteed by design. May not be 100% tested.
10. Relative to falling edge of TCK.
32
PRELIMINARY