80960JD Datasheet, PDF (15/61 Pages) Intel Corporation – EMBEDDED 32-BIT MICROPROCESSOR

A
80960JD
Table 4. Pin Description — Processor Control Signals, Test Signals and Power (Sheet 2 of 2)
NAME
FAIL
TCK
TDI
TDO
TRST
TMS
V_CC
V_CCPLL
V_SS
NC
TYPE
O
R(0)
H(Q)
P(1)
I
I
S(L)
O
R(Q)
HQ)
P(Q)
I
A(L)
I
S(L)
–
–
–
–
DESCRIPTION
FAIL indicates a failure of the processor’s built-in self-test performed during initial-
ization. FAIL is asserted immediately upon reset and toggles during self-test to
indicate the status of individual tests:
• When self-test passes, the processor deasserts FAIL and begins operation from
user code.
• When self-test fails, the processor asserts FAIL and then stops executing.
0 = self test failed
1 = self test passed
TEST CLOCK is a CPU input which provides the clocking function for IEEE 1149.1
Boundary Scan Testing (JTAG). State information and data are clocked into the
processor on the rising edge; data is clocked out of the processor on the falling edge.
TEST DATA INPUT is the serial input pin for JTAG. TDI is sampled on the rising edge
of TCK, during the SHIFT-IR and SHIFT-DR states of the Test Access Port.
TEST DATA OUTPUT is the serial output pin for JTAG. TDO is driven on the falling
edge of TCK during the SHIFT-IR and SHIFT-DR states of the Test Access Port. At
other times, TDO floats. TDO does not float during ONCE mode.
TEST RESET asynchronously resets the Test Access Port (TAP) controller function
of IEEE 1149.1 Boundary Scan testing (JTAG). When using the Boundary Scan
feature, connect a pulldown resistor between this pin and V_SS. If TAP is not used, this
pin must be connected to V_SS; however, no resistor is required. See Section 4.3,
Connection Recommendations (pg. 24).
TEST MODE SELECT is sampled at the rising edge of TCK to select the operation
of the test logic for IEEE 1149.1 Boundary Scan testing.
POWER pins intended for external connection to a V_CC board plane.
PLL POWER is a separate V_CC supply pin for the phase lock loop clock generator. It
is intended for external connection to the V_CC board plane. In noisy environments,
add a simple bypass filter circuit to reduce noise-induced clock jitter and its effects on
timing relationships.
GROUND pins intended for external connection to a V_{S S} board plane.
NO CONNECT pins. Do not make any system connections to these pins.
PRELIMINARY
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