80960JD Datasheet, PDF (28/61 Pages) Intel Corporation – EMBEDDED 32-BIT MICROPROCESSOR

80960JD
A
4.3 Connection Recommendations
For clean on-chip power distribution, V_CC and V_SS
pins separately feed the device’s functional units.
Power and ground connections must be made to all
80960JD power and ground pins. On the circuit
board, every V_CC pin should connect to a power
plane and every V_SS pin should connect to a ground
plane. Place liberal decoupling capacitance near the
80960JD, since the processor can cause transient
power surges.
4.4 DC Specifications
Pay special attention to the Test Reset (TRST) pin. It
is essential that the JTAG Boundary Scan Test
Access Port (TAP) controller initializes to a known
state whether it will be used or not. If the JTAG
Boundary Scan function will be used, connect a
pulldown resistor between the TRST pin and V_{S S}. If
the JTAG Boundary Scan function will not be used
(even for board-level testing), connect the TRST pin
to V_SS. Also, do not connect the TDI, TDO, and TCK
pins if the TAP Controller will not be used.
Pins identified as NC must not be connected in
the system.
Table 13. 80960JD DC Characteristics
Symbol
Parameter
Min
Typ
Max
V_IL
Input Low Voltage
-0.3
V_IH
Input High Voltage
2.0
V_OL
Output Low Voltage
V_OH
Output High Voltage
2.4
0.8
V_CC + 0.3
0.45
V_CC - 0.5
V_OLP
Output Ground Bounce
< 0.8
C_IN
Input Capacitance
PGA
12
PQFP
10
C_OUT
I/O or Output Capacitance
PGA
12
PQFP
10
C_CLK
CLKIN Capacitance
PGA
12
PQFP
10
NOTES:
1. Typical is measured with V_CC = 5.0V and temperature = 25 °C.
2. Not tested.
Units
V
V
V
V
V
pF
Notes
I_OL = 5 mA
I_OH = -1 mA
I_OH = -200 µA
(1,2)
f_CLKIN = f_MIN (2)
f_CLKIN = f_MIN (2)
pF
pF f_CLKIN = f_MIN (2)
24
PRELIMINARY