80960JD Datasheet, PDF (3/61 Pages) Intel Corporation – EMBEDDED 32-BIT MICROPROCESSOR

80960JD
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80960JD Microprocessor ...........................................................................................................0
80960JD Block Diagram ............................................................................................................2
132-Lead Pin Grid Array Bottom View - Pins Facing Up .......................................................... 13
132-Lead Pin Grid Array Top View - Pins Facing Down ........................................................... 14
132-Lead PQFP - Top View ..................................................................................................... 17
50 MHz Maximum Allowable Ambient Temperature ................................................................ 21
40 MHz Maximum Allowable Ambient Temperature ................................................................ 22
AC Test Load ............................................................................................................................ 33
Output Delay or Hold vs. Load Capacitance ............................................................................ 33
Rise and Fall Time Derating ..................................................................................................... 34
CLKIN Waveform ..................................................................................................................... 34
Output Delay Waveform for T_OV1 ............................................................................................. 35
Output Float Waveform for T_OF ................................................................................................ 35
Input Setup and Hold Waveform for T_IS1 and T_IH1 ................................................................... 36
Input Setup and Hold Waveform for T_IS2 and T_IH2 ................................................................... 36
Input Setup and Hold Waveform for T_IS3 and T_IH3 ................................................................... 37
Input Setup and Hold Waveform for T_IS4 and T_IH4 ................................................................... 37
Relative Timings Waveform for T_LXL and T_LXA ......................................................................... 38
DT/R and DEN Timings Waveform .......................................................................................... 38
TCK Waveform ......................................................................................................................... 39
Input Setup and Hold Waveforms for T_BSIS1 and T_BSIH1 ......................................................... 39
Output Delay and Output Float Waveform for T_BSOV1 and T_BSOF1 .......................................... 40
Output Delay and Output Float Waveform for T_BSOV2 and T_BSOF2 .......................................... 40
Input Setup and Hold Waveform for T_BSIS2 and T_BSIH2 ........................................................... 41
Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus ............................... 42
Burst Read and Write Transactions Without Wait States, 32-Bit Bus ...................................... 43
Burst Write Transactions With 2,1,1,1 Wait States, 32-Bit Bus ................................................ 44
Burst Read and Write Transactions Without Wait States, 8-Bit Bus ........................................ 45
Burst Read and Write Transactions With 1, 0 Wait States
and Extra Tr State on Read, 16-Bit Bus ................................................................................... 46
Bus Transactions Generated by Double Word Read Bus Request,
Misaligned One Byte From Quad Word Boundary, 32-Bit Bus, Little Endian ........................... 47
HOLD/HOLDA Waveform For Bus Arbitration .......................................................................... 48
Cold Reset Waveform .............................................................................................................. 49
Warm Reset Waveform ............................................................................................................ 50
Entering the ONCE State ......................................................................................................... 51
Summary of Aligned and Unaligned Accesses (32-Bit Bus) .................................................... 54
Summary of Aligned and Unaligned Accesses (32-Bit Bus) (Continued) ................................ 55
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PRELIMINARY