80960JD Datasheet, PDF (57/61 Pages) Intel Corporation – EMBEDDED 32-BIT MICROPROCESSOR

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80960JD
Table 22. Summary of n-Word Load and Store Accesses (n = 1, 2, 3, 4)
Address Offset
from Natural
Boundary in Bytes
Accesses on 8-Bit Bus
(WIDTH1:0=00)
+0 (aligned)
(n =1, 2, 3, 4)
• n burst(s) of 4 bytes
+1 (n =1, 2, 3, 4)
+5 (n = 2, 3, 4)
+9 (n = 3, 4)
+13 (n = 3, 4)
+2 (n =1, 2, 3, 4)
+6 (n = 2, 3, 4)
+10 (n = 3, 4)
+14 (n = 3, 4)
+3 (n =1, 2, 3, 4)
+7 (n = 2, 3, 4)
+11 (n = 3, 4)
+15 (n = 3, 4)
+4 (n = 2, 3, 4)
+8 (n = 3, 4)
+12 (n = 3, 4)
• byte access
• burst of 2 bytes
• n-1 burst(s) of 4 bytes
• byte access
• burst of 2 bytes
• n-1 burst(s) of 4 bytes
• burst of 2 bytes
• byte access
• n-1 burst(s) of 4 bytes
• burst of 2 bytes
• byte access
• n burst(s) of 4 bytes
Accesses on 16 Bit Bus
(WIDTH1:0=01)
• case n=1:
burst of 2 short words
• case n=2:
burst of 4 short words
• case n=3:
burst of 4 short words
burst of 2 short words
• case n=4:
2 bursts of 4 short words
• byte access
• short-word access
• n-1 burst(s) of 2 short words
• byte access
• short-word access
• n-1 burst(s) of 2 short words
• short-word access
• byte access
• n-1 burst(s) of 2 short words
• short-word access
• byte access
• n burst(s) of 2 short words
Accesses on 32 Bit
Bus (WIDTH1:0=10)
• burst of n word(s)
• byte access
• short-word access
• n-1 word access(es)
• byte access
• short-word access
• n-1 word access(es)
• short-word access
• byte access
• n-1 word access(es)
• short-word access
• byte access
• n word access(es)
PRELIMINARY
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