80960JD Datasheet, PDF (46/61 Pages) Intel Corporation – EMBEDDED 32-BIT MICROPROCESSOR

80960JD
A
5.0 BUS FUNCTIONAL WAVEFORMS
Figures 25 through 30 illustrate typical 80960JD bus transactions. Figure 31 depicts the bus arbitration
sequence. Figure 32 illustrates the processor reset sequence from the time power is applied to the device.
Figure 33 illustrates the processor reset sequence when the processor is in operation. Figure 34 illustrates the
processor ONCE sequence from the time power is applied to the device. Figures 35 and 36 also show
accesses on 32-bit buses. Tables 19 through 22 summarize all possible combinations of bus accesses across
8-, 16-, and 32-bit buses according to data alignment.
T_a T_d T_r
T_i
T _i T_a T_d
T_r
T _i T_i
CLKIN
AD31:0
ADDR
D
In
Invalid ADDR
DATA Out
ALE
ADS
A3:2
BE3:0
WIDTH1:0
10
10
D/ C
W/R
BLAST
DT/ R
DEN
RDYRCV
F_JF030A
Figure 25. Non-Burst Read and Write Transactions Without Wait States, 32-Bit Bus
42
PRELIMINARY