DT28F160S570 Datasheet, PDF (48/51 Pages) Intel Corporation – 5 VOLT FlashFile™ MEMORY

28F160S5/28F320S5
E
STS (R) ^VIH
V_IL
RP#
(P)
V_IH
V_IL
V_CC
V_CC1
V₀
P2
P1
P3
Figure 18. AC Waveform for Reset Operation
0609_18
Table 18. Reset AC Specifications⁽¹⁾
# Sym
Parameter
Notes Min Max Unit
P1 tPLPH RP# Pulse Low Time
100
ns
(If RP# is tied to VCC, this specification is not applicable)
P2 tPLRH RP# Low to Reset during Block Erase, Program, or Lock- 2,3
Bit Configuration
12
µs
P3 t5VPH VCC at 4.5 V to RP# High
100
ns
NOTES:
1. These specifications are valid for all product versions (packages and speeds).
2. If RP# is asserted while a block erase, program, or lock-bit configuration operation is not executing, the reset will complete
within tPLPH.
3. A reset time, tPHQV, is required from the latter of STS in RY/BY# mode or RP# going high until outputs are valid.
48
PRELIMINARY