DT28F160S570 Datasheet, PDF (28/51 Pages) Intel Corporation – 5 VOLT FlashFile™ MEMORY

28F160S5/28F320S5
E
suspended. The only other valid commands while
programming is suspended are Read Status
Register and Program Resume. After a Program
Resume command is written, the WSM will
continue the programming process. Status register
bits SR.2 and SR.7 will automatically clear and STS
in RY/BY# mode will return to VOL. After the
Program Resume command is written, the device
automatically outputs status register data when
read. VPP must remain at VPPH and VCC must
remain at VCC1/2 (the same VPP and VCC levels used
for programming) while in program suspend mode.
RP# must also remain at VIH (the same RP# level
used for programming). Refer to Figure 8 for the
Program Suspend/Resume Flowchart.
4.13 Set Block Lock-Bit Command
A flexible block locking and unlocking scheme is
enabled via a combination of block lock-bits. The
block lock-bits gate program and erase operations.
With WP# = VIH, individual block lock-bits can be
set using the Set Block Lock-Bit command.
Set block lock-bit is initiated using a two-cycle
command sequence. The Set Block Lock-Bit setup
along with appropriate block or device address is
written followed by the Set Block Lock-Bit Confirm
and an address within the block to be locked. The
WSM then controls the set lock-bit algorithm. After
the sequence is written, the device automatically
outputs status register data when read. The CPU
can detect the completion of the set lock-bit event
by analyzing STS in level RY/BY# mode or status
register bit SR.7.
When the set lock-bit operation is complete, status
register bit SR.4 should be checked. If an error is
detected, the status register should be cleared. The
CUI will remain in read status register mode until a
new command is issued.
This two-step sequence of setup followed by
execution ensures that lock-bits are not accidentally
set. An invalid Set Block Lock-Bit command will
result in status register bits SR.4 and SR.5 being
set to “1.” Also, reliable operations occur only when
VCC = VCC1/2 and VPP = VPPH. In the absence these
voltages, lock-bit contents are protected against
alteration.
A successful set block lock-bit operation requires
that WP# = VIH. If it is attempted with WP# = VIL,
the operation will fail and SR.1 and SR.4 will be set
to “1.” See Table 13 for write protection alternatives.
Refer to Figure 11 for the Set Block Lock-Bit
Flowchart.
4.14 Clear Block Lock-Bits
Command
All set block lock-bits are cleared in parallel via the
Clear Block Lock-Bits command. This command is
valid only when WP# = VIH.
The clear block lock-bits operation is initiated using
a two-cycle command sequence. A Clear Block
Lock-Bits setup command is written followed by a
Confirm command. Then, the device automatically
outputs status register data when read (see Figure
12). The CPU can detect completion of the clear
block lock-bits event by analyzing STS in level
RY/BY# mode or status register bit SR.7.
This two-step sequence of set-up followed by
execution ensures that block lock-bits are not
accidentally cleared. An invalid Clear Block
Lock-Bits command sequence will result in status
register bits SR.4 and SR.5 being set to “1.” Also, a
reliable clear block lock-bits operation can only
occur when VCC = VCC1/2 and VPP = VPPH. If a clear
block lock-bits operation is attempted while VPP ≤
VPPLK, SR.3 and SR.5 will be set to “1.” In the
absence of these voltages, the block lock-bits
contents are protected against alteration. A
successful clear block lock-bits operation requires
that WP# = VIH.
If a clear block lock-bits operation is aborted due to
VPP or VCC transitioning out of valid range or RP# or
WP# active transition, block lock-bit values are left
in an undetermined state. A repeat of clear block
lock-bits is required to initialize block lock-bit
contents to known values.
When the operation is complete, status register bit
SR.5 should be checked. If a clear block lock-bit
error is detected, the status register should be
cleared. The CUI will remain in read status register
mode until another command is issued.
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PRELIMINARY