DT28F160S570 Datasheet, PDF (11/51 Pages) Intel Corporation – 5 VOLT FlashFile™ MEMORY

E
3.2 Output Disable
With OE# at a logic-high level (V_IH), the device
outputs are disabled. Output pins DQ0–DQ15 are
placed in a high-impedance state.
3.3 Standby
CE0# or CE1# at a logic-high level (V_IH) places
the device in standby mode, substantially
reducing device power consumption. DQ0–DQ15
(or DQ0– DQ7 in x8 mode) outputs are placed in
a high-impedance state independent of OE#. If
deselected during block erase, programming, or
lock-bit configuration, the device continues
functioning and consuming active power until the
operation completes.
3.4 Deep Power-Down
RP# at VIL initiates the deep power-down mode.
In read mode, RP#-low deselects the memory,
places output drivers in a high-impedance state,
and turns off all internal circuits. RP# must be
held low for time tPLPH. Time tPHQV is required
after return from power-down until initial memory
access outputs are valid. After this wake-up
interval, normal operation is restored. The CUI
resets to read array mode, and the status register
is set to 80H.
During block erase, programming, or lock-bit
configuration modes, RP#-low will abort the
operation. STS in RY/BY# mode remains low
until the reset operation is complete. Memory
contents being altered are no longer valid; the
data may be partially corrupted after
programming or partially altered after an erase or
lock-bit configuration. Time tPHWL is required after
RP# goes to logic-high (V_IH) before another
command can be written.
28F160S5/28F320S5
It is important in any automated system to assert
RP# during system reset. When the system
comes out of reset, it expects to read from the
flash memory. Automated flash memories
provide status information when accessed during
block erase, programming, or lock-bit
configuration modes. If a CPU reset occurs with
no flash memory reset, proper CPU initialization
may not occur because the flash memory may be
providing status information instead of array data.
Intel’s Flash memories allow proper CPU
initialization following a system reset through the
use of the RP# input. In this application, RP# is
controlled by the same RESET# signal that
resets the system CPU.
3.5 Read Query Operation
The read query operation outputs block status,
Common Flash Interface (CFI) ID string, system
interface, device geometry, and Intel-specific
extended query information.
3.6 Read Identifier Codes
Operation
The read-identifier codes operation outputs the
manufacturer code, device code, and block lock
configuration codes for each block configuration
(see Figure 5). Using the manufacturer and
device codes, the system software can
automatically match the device with its proper
algorithms. The block-lock configuration codes
identify each block’s lock-bit setting.
PRELIMINARY
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