DT28F160S570 Datasheet, PDF (30/51 Pages) Intel Corporation – 5 VOLT FlashFile™ MEMORY

28F160S5/28F320S5
E
Table 15. Status Register Definition
WSMS
ESS
ECLBS BWSLBS
VPPS
BWSS
DPS
R
7
6
5
4
3
2
1
0
NOTES:
SR.7 = WRITE STATE MACHINE STATUS
1 = Ready
0 = Busy
Check STS in RY/BY# mode or SR.7 to determine
block erase, programming, or lock-bit configuration
completion. SR.6-0 are invalid while SR.7 = “0.”
SR.6 = ERASE SUSPEND STATUS
1 = Block erase suspended
0 = Block erase in progress/completed
SR.5 = ERASE AND CLEAR LOCK-BITS STATUS If both SR.5 and SR.4 are “1”s after a block erase
1 = Error in block erasure or clear lock-bits
or lock-bit configuration attempt, an improper
0 = Successful block erase or clear lock-bits command sequence was entered.
SR.4 = PROGRAM AND SET LOCK-BIT
STATUS
1 = Error in program or block lock-bit
0 = Successful program or set block lock-bit
SR.3 = V_PP STATUS
1 = V_PP low detect, operation abort
0 = V_PP OK
SR.3 does not provide a continuous indication of
VPP level. The WSM interrogates and indicates the
VPP level only after a block erase, program, or lock-
bit configuration operation. SR.3 reports accurate
feedback only when VPP = VPPH.
SR.2 = PROGRAM SUSPEND STATUS
1 = Program suspended
0 = Program in progress/completed
SR.1 = DEVICE PROTECT STATUS
1 = Block Lock-Bit and/or
WP# lock detected, operation abort
0 = Unlock
SR.1 does not provide a continuous indication of
block lock-bit values. The WSM interrogates the
block lock-bit, and WP# only after a block erase,
program, or lock-bit configuration operation. It
informs the system, depending on the attempted
operation, if the block lock-bit is set.
SR.0 = RESERVED FOR FUTURE
ENHANCEMENTS
SR.0 is reserved for future use and should be
masked when polling the status register.
Table 16. Extended Status Register Definition
WBS
R
R
R
R
R
R
R
7
6
5
4
3
2
1
0
XSR.7 = WRITE BUFFER STATUS
1 = Write to buffer available
0 = Write to buffer not available
XSR.6–0 = RESERVED FOR FUTURE
ENHANCEMENTS
NOTES:
After a Write to buffer command, XSR.7 indicates
that another Write to buffer command is possible.
SR.6–0 are reserved for future use and should be
masked when polling the status register
30
PRELIMINARY