DT28F160S570 Datasheet, PDF (29/51 Pages) Intel Corporation – 5 VOLT FlashFile™ MEMORY

E
28F160S5/28F320S5
Operation
Program and
Block Erase
Full Chip Erase
Set or Clear
Block Lock-Bit
Block
Lock-
Bit
0
1
0,1
X
X
Table 13. Write Protection Alternatives
WP#
Effect
VIL or VIH
VIL
VIH
VIL
VIH
VIL
VIH
Block erase and programming enabled
Block is locked. Block erase and programming disabled
Block Lock-Bit override. Block erase and programming enabled
All unlocked blocks are erased
Block Lock-Bit override. All blocks are erased
Set or clear block lock-bit disabled
Set or clear block lock-bit enabled
Table 14. Configuration Coding Definitions
Reserved
Pulse on
Write
Complete
Pulse on
Erase
Complete
bits 7–2
bit 1
bit 0
DQ7–DQ2 = Reserved
DQ7–DQ2 are reserved for future use.
DQ1/DQ0 = STS Pin Configuration Codes
00 = default, level mode RY/BY#
(device ready) indication
01 = pulse on Erase complete
10 = pulse on Flash Program complete
11 = pulse on Erase or Program Complete
Configuration Codes 01b, 10b, and 11b are all pulse
mode such that the STS pin pulses low then high
when the operation indicated by the given
configuration is completed.
Configuration Command Sequences for STS pin
configuration (masking bits D7–D2 to 00h) are as
follows:
Default RY/BY# level mode
B8h, 00h
ER INT (Erase Interrupt):
B8h, 01h
Pulse-on-Erase Complete
PR INT (Program Interrupt):
B8h, 02h
Pulse-on-Flash-Program Complete
ER/PR INT (Erase or Program Interrupt): B8h, 03h
Pulse-on-Erase or Program Complete
default (DQ1/DQ0 = 00) RY/BY#, level mode
—used to control HOLD to a memory controller to
prevent accessing a flash memory subsystem while
any flash device's WSM is busy.
configuration 01
ER INT, pulse mode⁽¹⁾
—used to generate a system interrupt pulse when
any flash device in an array has completed a block
erase or sequence of queued block erases. Helpful
for reformatting blocks after file system free space
reclamation or ‘cleanup’
configuration 10
PR INT, pulse mode⁽¹⁾
—used to generate a system interrupt pulse when
any flash device in an array has complete a
program operation. Provides highest performance
for servicing continuous buffer write operations.
configuration
ER/PR INT, pulse mode⁽¹⁾
—used to generate system interrupts to trigger
servicing of flash arrays when either erase or flash
program operations are completed when a common
interrupt service routine is desired.
NOTE:
1. When the device is configured in one of the pulse modes, the STS pin pulses low with a typical pulse width of 250 ns.
PRELIMINARY
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