DT28F160S570 Datasheet, PDF (10/51 Pages) Intel Corporation – 5 VOLT FlashFile™ MEMORY

28F160S5/28F320S5
bit configuration can be stored in any block. This
code is copied to and executed from system
RAM during flash memory updates. After
successful completion, reads are again possible
via the Read Array command. Block erase
suspend allows system software to suspend a
block erase to read or write data from any other
block. Program suspend allows system software
to suspend a program to read data from any
other flash memory array location.
2.1 Data Protection
Depending on the application, the system
designer may choose to make the VPP power
supply switchable or hardwired to VPPH. The
device supports either design practice, and
encourages optimization of the processor-
memory interface.
When VPP ≤ VPPLK, memory contents cannot be
altered. When high voltage is applied to VPP, the
two-step block erase, program, or lock-bit
configuration command sequences provide
protection from unwanted operations. All write
functions are disabled when VCC voltage is below
the write lockout voltage VLKO or when RP# is at
VIL. The device’s block locking capability
provides additional protection from inadvertent
code or data alteration.
E
3.0 BUS OPERATION
The local CPU reads and writes flash memory in-
system. All bus cycles to or from the flash
memory conform to standard microprocessor bus
cycles.
3.1 Read
Block information, query information, identifier
codes and status registers can be read
independent of the V_PP voltage.
The first task is to place the device into the
desired read mode by writing the appropriate
read-mode command (Read Array, Query, Read
Identifier Codes, or Read Status Register) to the
CUI. Upon initial device power-up or after exit
from deep power-down mode, the device
automatically resets to read array mode. Control
pins dictate the data flow in and out of the
component. CE0#, CE1# and OE# must be driven
active to obtain data at the outputs. CE0# and
CE1# are the device selection controls, and,
when both are active, enable the selected
memory device. OE# is the data output (DQ0–
DQ15) control: When active it drives the selected
memory data onto the I/O bus. WE# must be at
V_IH and RP# must be at V_IH. Figure 16 illustrates
a read cycle.
3FFFFF
3F0000
16-Mbit: A[_20-0]
32-Mbit: A[_21-0]
64-Kbyte Block 63
1FFFFF
1F0000
16-Mbit: A[_20-1]
32-Mbit: A[_21-1]
32-Kword Block 63
1FFFFF
1F0000
64-Kbyte Block 31
01FFFF
010000
00FFFF
000000
64-Kbyte Block 1
64-Kbyte Block 0
Byte-Wide (x8) Mode
0FFFFF
0F8000
32-Kword Block 31
32 Mbit
00FFFF
008000
007FFF
000000
32-Kword Block 1
32-Kword Block 0
Word-Wide (x16) Mode
16 Mbit
0609_04
Figure 4. Memory Map
10
PRELIMINARY