82562EZ Datasheet, PDF (30/40 Pages) Intel Corporation – 82562EZ 10/100 Mbps Platform LAN Connect (PLC)

82562EZ — Networking Silicon
5.3.10
5.3.11
Register 25: 10BASE-T Transmit Jabber Detect Counter Bit
Definitions
Bit(s)
Name
15:0 Jabber Detect
Counter
Description
This is a 16-bit counter that increments for each jab-
ber detection event. The counter stops when it is full
and self-clears on read.
Default
--
R/W
RO
SC
Register 27: PHY Unit Special Control Bit Definitions
Bit(s)
Name
Description
15:6 Reserved
5
Switch Probe
Mapping
These bits are reserved and should be set to a con-
stant 0.
This bit switches the mapping on the LEDs. The LED
mapping is described below in bits 2:0, LED Switch
Control. This bit should always be set to 0b.
4
Reserved
This bit is reserved and should be set to 0.
3
100BASE-TX
This bit enables the carrier sense disconnection while
Receive Jabber the PHY is in jabber mode at 100 Mbps speed.
Disable
2:0
LED Switch Con- Value
ACTLED# LILED#
trol
000
Activity Link
001
Speed
Collision
010
Speed
Link
011
Activity Collision
100
Off
Off
101
Off
On
110
On
Off
111
On
On
Default
0
R/W
RO
0
RW
0
RO
0
RW
000 RW
24
Datasheet