82562EZ Datasheet, PDF (29/40 Pages) Intel Corporation – 82562EZ 10/100 Mbps Platform LAN Connect (PLC)

Networking Silicon — 82562EZ
5.3.5
5.3.6
5.3.7
5.3.8
5.3.9
Register 20: 100BASE-TX Receive Disconnect Counter Bit Definitions
Bit(s)
Name
Description
15:0 Disconnect Event This field contains a 16-bit counter that increments for
each disconnect event. The counter stops when it is
full and self-clears on read
Default
--
R/W
RO
SC
Register 21: 100BASE-TX Receive Error Frame Counter Bit
Definitions
Bit(s)
Name
15:0 Receive Error
Frame
Description
This field contains a 16-bit counter that increments
once per frame for any receive error condition (such
as a symbol error or premature end of frame) in that
frame. The counter stops when it is full and self-clears
on read.
Default
--
R/W
RO
SC
Register 22: Receive Symbol Error Counter Bit Definitions
Bit(s)
Name
15:0 Symbol Error
Counter
Description
This field contains a 16-bit counter that increments for
each symbol error. The counter stops when it is full
and self-clears on read.
In a frame with a bad symbol, each sequential six bad
symbols count as one.
Default
--
R/W
RO
SC
Register 23: 100BASE-TX Receive Premature End of Frame Error
Counter Bit Definitions
Bit(s)
Name
Description
15:0 Premature End of This field contains a 16-bit counter that increments for
Frame
each premature end of frame event. The counter
stops when it is full and self-clears on read.
Default
--
R/W
RO
SC
Register 24: 10BASE-T Receive End of Frame Error Counter Bit
Definitions
Bit(s)
Name
15:0 End of Frame
Counter
Description
This is a 16-bit counter that increments for each end
of frame event. The counter stops when it is full and
self-clears on read.
Default
--
R/W
RO
SC
Datasheet
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