82562EZ Datasheet, PDF (13/40 Pages) Intel Corporation – 82562EZ 10/100 Mbps Platform LAN Connect (PLC)

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3.7
Networking Silicon — 82562EZ
LED Pins
Pin Name
LILED#
ACTLED#
SPDLED#
Type
O
O
O
Description
Link Integrity LED. The LED is active low and the Link Integrity LED pin indicates
link status in either 10BASE-T or 100BASE-TX mode. If a link is present in either
mode, the LILED is asserted.
Activity LED. The LED is active low and the Activity LED signal indicates either
receive or transmit activity. When no activity is present, the LED is off. The Activity
LED will flicker when activity is present. The flicker rate depends on the activity load.
The individual address LED control bit (Word A hexadecimal, bit 4) in the ICH4
EEPROM can select the ACTLED# behavior. It controls the Activity LED (ACTLED#)
functionality in Wake on LAN (WOL) mode.
0 = In WOL mode, the ACTLED# is activated by the transmission and reception of
broadcast and individual address match packets.
1 = In WOL mode, the ACTLED# is activated by the transmission and reception of
individual address match packets only.
This bit is configured by the OEM and is activated by a transmission and reception of
individual address match packets.
Speed LED. The LED is active low and the Speed LED signal indicates the speed of
operation, either 10 Mbps or 100 Mbps. The Speed LED is on during 100BASE-TX
operation and off in 10BASE-T mode.
Miscellaneous Control Pins
Pin Name Type
Description
ADV10
I
ISOL_TCK I
ISOL_TI
I
ISOL_EXEC I
TOUT
O
TESTEN
I
Advertise 10 Mbps Only. The Advertise 10 Mbps Only signal is asserted high, and
the 82562EZ advertises only 10BASE-T technology during Auto-Negotiation
processes in this state. Otherwise, the 82562EZ advertises all of its technologies.
Note: ADV10 has an internal pull-down resistor.
Test Clock. The Test Clock signal sets the device into asynchronous test mode in
conjunction with the Test Input, Test Execute and Test Enable pins (refer to Table 1,
“82562EZ Hardware Configuration”).
In the manufacturing test mode, it acts as the test clock.
Note: ISOL_TCK has an internal pull-down resistor.
Test Input. The Test Input signal sets the device into asynchronous test mode in
conjunction with the Test Clock, Test Execute and Test Enable pins (refer to Table 1,
“82562EZ Hardware Configuration”).
In the manufacturing test mode, it acts as the test data input pin.
Note: ISOL_TI has an internal pull-down resistor.
Test Execute. The Test Execute signal sets the device into asynchronous test mode
in conjunction with the Test Clock, Test Input, and Test Enable pins (refer to Table 1,
“82562EZ Hardware Configuration”).
In the manufacturing test mode, it places the command that was entered through the
TI pin in the instruction register.
Note: ISOL_EXEC has an internal pull-down resistor.
Test Output. The Test Output pin is used for Boundary XOR scan output. In the
manufacturing test mode, it acts as the test output port.
Test Enable. The Test Enable pin is used to enable test mode and should be pulled
down to V_SS to allow XOR Tree test mode.
Datasheet
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