82562EZ Datasheet, PDF (11/40 Pages) Intel Corporation – 82562EZ 10/100 Mbps Platform LAN Connect (PLC)

3.0
3.1
3.2
3.3
Networking Silicon — 82562EZ
82562EZ Signal Descriptions
Signal Type Definitions
Type
I
O
I/O
MLT
B
DPS
APS
Name
Description
Input
Input pin to the 82562EZ.
Output
Output pin from the 82562EZ.
Input/Output Multiplexed input and output pin to and from the 82562EZ.
Multi-level
analog I/O
Multi-level analog pin used for input and output.
Bias
Bias pin used for ground connection through a resistor or an external voltage
reference.
Digital Power
Supply
Digital power or ground pin for the 82562EZ.
Analog Power
Supply
Analog power or ground pin for the 82562EZ.
Twisted Pair Ethernet (TPE) Pins
Pin Name
TDP
TDN
RDP
RDN
Type
MLT
MLT
Description
Transmit Differential Pair. The transmit differential pair sends serial bit streams to
the unshielded twisted pair (UTP) cable. The differential pair is a two-level signal in
10BASE-T (Manchester) mode and a three-level signal in 100BASE-TX mode (MLT-
3). These signals directly interface with the isolation transformer.
Receive Differential Pair. The receive differential pair receive the serial bit stream
from an unshielded twisted pair (UTP) cable. The differential pair is a two-level signal
in 10BASE-T mode (Manchester) or a three-level signal in 100BASE-TX mode (MLT-
3). These signals directly interface with an isolation transformer.
External Bias Pins
Pin Name Type
Description
RBIAS100 B
RBIAS10
B
Reference Bias Resistor (100 Mbps). This pin should be connected to a pull-down
resistor.^a
Reference Bias Resistor (10 Mbps). This pin should be connected to a pull-down
resistor.^a
a. Based on some board designs, RBIAS100 and RBIAS10 values may need to be increased/decreased to compensate for high/
low MDI transmit amplitude. See the 82562EZ(EX)/82551ER(IT) & 82541ER Combined Footprint LOM Design Guide for more
information.
Datasheet
5