82562EZ Datasheet, PDF (24/40 Pages) Intel Corporation – 82562EZ 10/100 Mbps Platform LAN Connect (PLC)

82562EZ — Networking Silicon
5.1.2
Bit(s)
10
Name
Isolate
9
Restart Auto-
Negotiation
8
Duplex Mode
7
Collision Test
6:0
Reserved
Description
Default R/W
This bit allows the PHY to isolate the medium indepen-
dent interface. The PHY is disconnected from the LAN
Connect block on both the transmit and receive side.
0 = Normal operation
1 = Isolates internal medium independent interface
0
RW
This bit restarts the Auto-Negotiation process and is self-
clearing.
0 = Normal operation
1 = Restart Auto-Negotiation process
0
RW
SC
This bit controls the duplex mode when Auto-Negotiation
is disabled. When Auto-Negotiation is enabled this bit is
read only and always equals 1b.
When the PHY is placed in Loopback mode, the behavior
of the PHY shall not be affected by the status of this bit.
0 = Half Duplex
1 = Full Duplex
0
RW/
RO
This bit is not used in the 82562EZ and has a default
value of 1b. (If it is used in other devices, it forces a colli-
sion in response to the assertion of the transmit enable
signal.)
1
RW
These bits are reserved and should be set to 0000000b.
0
RW
Register 1: Status Register Bit Definitions
Bit(s)
Name
15
Reserved
14
100BASE-TX
Full-duplex
13
100 Mbps Half-
duplex
12
10 Mbps Full-
duplex
11
10 Mbps Half-
duplex
10:7 Reserved
6
Management
Frames Pream-
ble Suppression
Description
This bit is reserved and should be set to 0b.
This bit enables 100BASE-TX full-duplex operation
and is dependent on ADV10. If ADV10 is active, the
default value is 0.
0 = PHY unable to perform full-duplex 100BASE-TX
1 = PHY able to perform full-duplex 100BASE-TX
This bit enables 100BASE-TX half-duplex operation
and is dependent on ADV10. If ADV10 is active, the
default value is 0.
0 = PHY unable to perform half-duplex 100BASE-TX
1 = PHY able to perform half-duplex 100BASE-TX
This bit enables 10BASE-T full duplex operation.
0 = PHY unable to perform full-duplex 10BASE-T
1 = PHY able to perform full-duplex 10BASE-T
This bit enables 10BASE-T half-duplex operation.
0 = PHY unable to perform half-duplex 10BASE-T
1 = PHY able to perform half-duplex 10BASE-T
These bits are reserved and should be set to 0000b.
This bit allows the 82562EZ to receive management
frames with suppressed preamble.
0 = PHY will not accept management frames with
preamble suppressed
1 = PHY will accept management frames with
preamble suppressed
Default
0
1
R/W
RO
RO
1
RO
1
RO
1
RO
0
RO
0
RO
18
Datasheet