82562EZ Datasheet, PDF (21/40 Pages) Intel Corporation – 82562EZ 10/100 Mbps Platform LAN Connect (PLC)

Networking Silicon — 82562EZ
The 82562EZ can enter a reduced power state manually through bit 11 of register 0. This bit is ORed with the LAN
Connect power down bit, which allows the 82562EZ to enter a reduced power state.
Table 4. Register 0: Control Data
Bit
11
Name
Reduced Power Down
Description
Read/Write
0 = Reduced power down disabled (normal
operation; default)
1 = Reduced power down enabled
Read/Write
4.5
Reset
When 82562EZ’s Reset signal (RSTSYNC) is asserted for at least 500 µseconds, all internal circuits are reset. The
82562EZ can also be reset through the MII management register reset bit (register 0, bit 15).
4.6
LAN Connect Interface
The 82562EZ supports the LAN connect interface as specified in the LAN Connect Interface Specification. The
LAN Connect is the I/O Control Hub 4(ICH4) interface to the 82562EZ. The 8-pin interface incorporates all MII
and MII management functionality and includes the reset functionality as well.
4.6.1
LAN Connect Clock
The 82562EZ drives a 50 MHz or 5 MHz clock to the MAC depending on the selected technology (100BASE-TX
or 10BASE-T, respectively). The 82562EZ does not stop the LAN Connect clock for any reason. During reduced
power mode, the 82562EZ drives a 5 MHz clock.
4.6.2
LAN Connect Reset
To determine the type of signal on the PLC Reset/Synchronization pin, the 82562EZ filters out pulses that are less
than 200 nanoseconds. To reset the 82562EZ, the pulse should be longer than 500 µseconds.
4.7
LED Functionality
Table 5. LED Functionality
LED Driver
ACTLED#
SPDLED#
LILED#
Function
Activity
Speed
Link valid
Description
The driver blinks at a rate related to the utilization. The blinking occurs during
transmission or reception of a frame.
The driver is low for 100BASE-TX operation and high for 10BASE-T mode.
The driver is low when a valid link is present.
Datasheet
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