82562EZ Datasheet, PDF (28/40 Pages) Intel Corporation – 82562EZ 10/100 Mbps Platform LAN Connect (PLC)

82562EZ — Networking Silicon
5.3.3
5.3.4
Bit(s)
Name
Description
11
Valid Link
0 = Normal operation
1 = 100BASE-TX valid link
10
Symbol Error
0 = Normal operation
Enable
1 = Symbol error output is enabled
9
Carrier Sense
This bit controls the receive 100 carrier sense disable
Disable
function.
0 = Carrier sense enabled
1 = Carrier sense disabled
8
Disable Dynamic 0 = Dynamic Power-Down enabled
Power-Down
1 = Dynamic Power-Down disabled
7
Auto-Negotiation 0 = Auto-Negotiation normal mode
Loopback
1 = Auto-Negotiation loopback
6
MDI Tri-State
0 = Normal operation
1 = MDI Tri-state (transmit driver tri-states)
5
Force Polarity
0 = Normal polarity
1 = Reversed polarity
4
Auto Polarity Dis- 0 = Normal polarity operation
able
1 = Auto Polarity disabled
3
Squelch Disable 0 = Normal squelch operation
1 = 10BASE-T squelch test disable
2
Extended
Squelch
1 = 10BASE-T Extended Squelch control enabled
0 = 10BASE-T Extended Squelch control disabled
1
Link Integrity Dis- 0 = Normal Link Integrity operation
able
1 = Link disabled
0
Jabber Function 0 = Normal Jabber operation
Disable
1 = Jabber disabled
Default
0
R/W
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
0
RW
Register 18: PHY Address Register
Bit(s)
Name
15:5 Reserved
4:0
PHY Address
Description
These bits are reserved and should be set to a con-
stant 0.
These bits are set to the PHY’s address.
Default
0
R/W
RO
00001 RO
Register 19: 100BASE-TX Receive False Carrier Counter Bit
Definitions
Bit(s)
Name
15:0 Receive False
Carrier
Description
These bits are used for the false carrier counter.
Default
--
R/W
RO
SC
22
Datasheet