82562EZ Datasheet, PDF (27/40 Pages) Intel Corporation – 82562EZ 10/100 Mbps Platform LAN Connect (PLC)

Networking Silicon — 82562EZ
5.3
5.3.1
5.3.2
Medium Dependent Interface Registers 16 through 31
Register 16: PHY Status and Control Register Bit Definitions
Bit(s)
Name
Description
15:14 Reserved
These bits are reserved and should be set to 00b.
13
Reduced Power This bit disables the automatic reduced power down.
Down Disable
0 = Enable automatic reduced power down
1 = Disable automatic reduced power down
12
Reserved
This bit is reserved and should be set to 0b.
11
Receive De-Seri- This bit indicates status of the 100BASE-TX Receive
alizer In-Sync
De-Serializer In-Sync.
Indication
10
100BASE-TX
This bit indicates the power state of 100BASE-TX
Power-Down
PHY unit.
0 = Normal operation
1 = Power-down
9
10BASE-T
This bit indicates the power state of 10BASE-T PHY
Power-Down
unit.
0 = Normal operation
1 = Power-Down
8
Polarity
This bit indicates 10BASE-T polarity.
0 = Normal polarity
1 = Reverse polarity
7
Reserved
This bit is reserved and should be set to 0b.
6:2
PHY Address
These bits contain the sampled PHY address.
1
Speed
This bit indicates the Auto-Negotiation result.
0 = 10 Mbps
1 = 100 Mbps
0
Duplex Mode
This bit indicates the Auto-Negotiation result.
0 = Half-duplex
1 = Full-duplex
Default
00
1
R/W
RW
RW
0
RW
--
RO
1
RO
1
RO
--
RO
0
RO
--
RO
--
RO
--
RO
Register 17: PHY Unit Special Control Bit Definitions
Bit(s)
Name
Description
15
Scrambler By-
0 = Normal operations
pass
1 = By-pass scrambler
14
By-pass 4B/5B 0 = Normal operation
1 = 4 bit to 5 bit by-pass
13
Force Transmit H- 0 = Normal operation
Pattern
1 = Force transmit H-pattern
12
Force 34 Transmit 0 = Normal operation
Pattern
1 = Force 34 transmit pattern
Default
0
R/W
RW
0
RW
0
RW
0
RW
Datasheet
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