HYE18P32161AC Datasheet, PDF (9/33 Pages) Infineon Technologies AG – 32M Asynchronous/Page CellularRAM

HYE18P32161AC(-/L)70/85
32M Asynch/Page CellularRAM
Overview
1.2
General Description
The 32M Asynchronous/Page CellularRAM (CellularRAM) is is the competitive alternative to today’s SRAM based
solutions in wireless applications, such as cellular phones. With its high density 1T1C-cell concept and highly
optimized low power design, the CellularRAM is the advanced economic solution for the growing memory demand
in baseband IC designs. SRAM-pin compatibility, refresh-free operation and extreme low power design makes a
drop-in replacement in legacy systems an easy procedure.
Low power feature of Partial Array Self Refresh (PASR) allows the user to dynamically scale the active
(=refreshed) memory to his needs and to adapt the refresh rate to the actual system environment. That is no power
penalty is paid in case only portions of the total available memory capacity is used (e.g. 8Mb out of 32Mb).
The CellularRAM is available in two package options, in the SRAM compatible FBGA 48-ball package and with an
enhanced feature set in a FBGA 54-ball package. For the advanced 54-ball device please refer to the
corresponding data sheet (HYE18P32160AC).
The CelllularRAM can be powered from a single 1.8V power supply feeding the core and the output drivers.
Feeding the I/Os with a separate voltage supply the CelllularRAM can be easily adapted to systems operating in
an I/O voltage range from 1.8V to 3.0V. The chip is fabricated in Infineon Technologies advanced 0.14µm low
power process technology.
The configuration of interfacing CellularRAM is illustrated in Figure 1. Data byte control (UB, LB) is featured in all
modes and provides dedicated lower and upper byte access.
CS1
WE
OE
UB
LB
ZZ
A20-A0
FBGA-48
DQ15-DQ0
CS1
WE
OE
UB
LB
ZZ
A20-A0
FBGA-48
DQ15-DQ0
1.8V VDD & VDDQ
1.8V VDD
2.5V/ 3.0V VDDQ
Figure 1 CellularRAM - Interface Configuration Options
The CellularRAM comes in a P-VFBGA-48 package.
Data Sheet
9
V2.0, 2003-12-16