HYE18P32161AC Datasheet, PDF (30/33 Pages) Infineon Technologies AG – 32M Asynchronous/Page CellularRAM

HYE18P32161AC(-/L)70/85
32M Asynch/Page CellularRAM
Appendix A: Low-Frequency Mode
5
Appendix A: Low-Frequency Mode
5.1
Asynchronous Access
Depending on the random access frequency two cases are distinguished:
High Frequency Mode (≥ 100 kHz):
There are no t_RC max. time nor CS1/OE max. low time restrictions during subsequent random read or write
accesses.
Low Frequency Mode (< 100 kHz):
There are no t_RC max. time nor CS1/OE max. low time restrictions if all control signals (CS1, OE, WE, UB/LB)
follow the modified timing as shown below, see attached timing diagram and timing table. There is no extra mode
register setting necessary.
A20-A0
CS1
WE
DQ<15:0>
t_ARV
ADDRESS
t_AWV
t_AA
t_WPV
t_DWV
Data Valid
Data Valid
Figure 19 Low Frequency Mode
Parameter
Address stable time for read access
Address stable overlap with write
pulse
Write pulse width
Data to write time overlap
Symbol
t_ARV
t_AWV
t_WPV
t_DWV
Min.
70
70
70
70
70
Max.
–
–
–
–
Min.
85
85
85
Max.
–
–
85
–
85
–
Unit Notes
ns
–
ns
–
ns
–
ns
–
Data Sheet
30
V2.0, 2003-12-16