HYE18P32161AC Datasheet, PDF (8/33 Pages) Infineon Technologies AG – 32M Asynchronous/Page CellularRAM

32M Asynchronous/Page CellularRAM
CellularRAM
HYE18P32161AC-70/L70
HYE18P32161AC-85/L85
1
Overview
1.1
Features
• High density (1T1C-cell) Synchronous 32-Mbit Pseudo-Static RAM
• Designed for cell phone applications (CellularRAM)
• Functional-compatible to conventional low power asynchronous SRAM devices
• Organization 2M × 16
• Refresh-free operation
• 1.8 V single power supply (V_DD and V_DDQ)
• Support of 2.5V and 3.0V I/O voltage options (V_DDQ)
• Low power optimized design
– I_STANDBY = 90 µA for L-part and 120 µA for standard part (32M), data retention mode
– I_DPD = < 25 µA (32M), non-data retention mode
• Low power features (partly adopted from the JEDEC standardized low power SDRAM specifications)
– Temperature Compensated Self-Refresh (TCSR)
– Partial Array Self-Refresh (PASR)
– Deep Power Down Mode (DPD)
• 70 ns random access cycle time, 20 ns page mode (read only) cycle time
• Byte read/write control by UB/LB
• Wireless operating temperature range from -25 °C to +85 °C
• P-VFBGA-48 chip-scale package (8 × 6 ball grid)
Table 1 Product Selection
HYE18P32161AC
Min. Random Cycle time (tRC)
Min. Page Read Cycle time (tPC)
Operating current (Icc1)
Stand-by current (Icc2)
Ordering Info
-70
-85
70ns
85ns
20ns
25ns
20mA
17mA
120uA
L70
L85
70ns
85ns
20ns
25ns
20mA
17mA
90uA
(Contact Factory)
HYE 18 P 3216 1 A C
Extended Temp. part
32M (x16 Org)
Chip Scale Package
Design Revision number
V_DD = 1.8 V typ.
PSRAM product
Device Type
1: Asynch/Page (48-ball)
Data Sheet
8
V2.0, 2003-12-16