HYE18P32161AC Datasheet, PDF (17/33 Pages) Infineon Technologies AG – 32M Asynchronous/Page CellularRAM

HYE18P32161AC(-/L)70/85
32M Asynch/Page CellularRAM
Functional Description
Field
PASR
Res
Bits
[2:0]
20,
[18:8],
3
Type¹⁾ Description
w
Partial Array Self Refresh
The 3-bit PASR field is used to specify the active memory array. The active memory
array will be kept periodically refreshed whereas the disabled parts will be excluded
from refresh and previously stored data will get lost. The normal operation still can be
executed in disabled array, but stored data is not guaranteed. This way the customer
can dynamically adapt the memory capacity in steps of 8 Mbit (4Mbit at the lowest) to
one’s need without paying a power penalty. Please refer to Figure 7.
000 entire memory array (default)
001 lower 1/2 of the memory array (16 Mb)
010 lower 1/4 of the memory array (8 Mb)
011 lower 1/8 of the memory array (4 Mb)
100 zero
101 upper 1/2 of the memory array (16 Mb)
110 upper 1/4 of the memory array (8 Mb)
111 upper 1/8 of the memory array (4 Mb)
w
Reserved
must be set to ‘0’
1) w: write-only access
2.3.1 Partial Array Self Refresh (PASR)
By applying PASR the user can dynamically customize the memory capacity to one’s actual needs in normal
operation mode and standby mode. With the activation of PASR there is no longer a power penalty paid for the
larger CellularRAM memory capacity in case only e.g. 8 MB are used by the host system.
Bit2 down to bit0 specify the active memory array and its location (starting from bottom or top). The memory parts
not used are powered down immediately after the mode register has been programmed. Advice for the proper
register setting including the address ranges is given in Figure 7.
1FFFFFh
17FFFFh
0FFFFFh
07FFFFh
011 010 001 000 ^000000h
4M
8M 16M 32M
PA SR .B it2 ,1 ,0
8M
8M
8M
8M
1FFFFFh
PASR.Bit2,1,0
16M 8M
4M
0M
101 110 111 100
180000h
100000h
080000h
000000h
Figure 7 PASR Programming Scheme
PASR is activated, i.e. the memory parts not used are powered down, after ZZ has been held low for more than
10µs. In PASR state no READ or WRITE commands are recognized. To resume WRITE or READ operations, the
device must exit PASR by taking ZZ to high level voltage again.
Pre-condition to enter PASR on ZZ low is that the Deep Power Down mode has been disabled before via
RCR.Bit4= 1.
Figure 8 shows an exemplary PASR configuration where it is assumed that the application uses max. 8 Mbit out
of 32 Mbit.
Data Sheet
17
V2.0, 2003-12-16