HYE18P32161AC Datasheet, PDF (21/33 Pages) Infineon Technologies AG – 32M Asynchronous/Page CellularRAM

HYE18P32161AC(-/L)70/85
32M Asynch/Page CellularRAM
Functional Description
2.4.1 Page Read Mode
If activated by RCR.Bit7 page mode allows to toggle the four lower address bits (A3 to A0) to perform subsequent
random read accesses (max. 16-words by A3 - A0) at much faster speed than 1^st read access. Page mode
operation supports only read access in CellularRAM. As soon as page mode is activated, CS1 low time restriction
(t_CSL) applies. In case of CS1 staying low longer than t_CSL limit, then it is alternative way to toggle non-page address
(A20 - A4) no later than t_CSL,max. Therefore the usage of page mode is only recommended in systems which can
respect this limitation.
Please see also application note on Page 30.
A20-A4
A3-A0
CS1
UB, LB
WE
OE
DQ15-DQ0
ADDRESS
t_AA
t_CO
t_RC
ADDRESS
t_PC
ADR
ADR
ADR
ADR
t_CSL
t_BLZ
t_OLZ
t_LZ
Don't Care
t_OH
Data
Data
t_PAA
Data
Data
Data
t_HZ
t_BHZ
t_OHZ
Figure 11 Asynchronous Page Read Mode (ZZ = V_IH)
Data Sheet
21
V2.0, 2003-12-16