HYE18P32161AC Datasheet, PDF (11/33 Pages) Infineon Technologies AG – 32M Asynchronous/Page CellularRAM

HYE18P32161AC(-/L)70/85
32M Asynch/Page CellularRAM
Overview
1.4
HYE18P32161AC(-/L)70/85 Ball Definition and Description
Table 2 Ball Description - HYE18P32161AC(-/L)70/85
Ball
Type Detailed Function
CS1
Input Chip Select
CS1 enables the command decoder when low and disables it when high. When the
command decoder is disabled new commands are ignored, addresses are don’t care and
outputs are forced to high-Z. Internal operations, however, continue. For the details
please refer to the command tables in Chapter 1.6.
OE
Input Output Enable
OE controls DQ output driver. OE low drives DQ, OE high sets DQ to high-Z.
WE
Input Write Enable
WE set to low while CS is low initiates a write command.
UB, LB
Input
Upper/Lower Byte Enable
UB enables the upper byte DQ15-8 (resp. LB DQ7 … 0) during read/write operations.
UB (LB) deassertion prevents the upper (lower) byte from being driven during read or
being written.
ZZ
Input
Deep Power Down Enable/ Set Control Register
Strapping ZZ to low for more than 10µs the device is put to deep power down mode. If a write
access is initiated instantly (<500ns) after ZZ has been asserted to low access to the refresh
configuration register is given. By applying the SET CONTROL REGISTER (SCR) command
(see Table 3) the address bus is then loaded into the refresh control register.
A <20:0> Input
Address Inputs
During a Control Register Set operation, the address inputs define the register settings.
DQ <15:0> I/O
Data Input/Output
The DQ signals 0 to 15 form the 16-bit data bus.
1 × V_DD
1 × V_SS
1 × V_DDQ
1 × V_SSQ
1 × NC
Power
Supply
Power
Supply
–
Power Supply, Core
Power and Ground for the internal logic.
Power Supply, I/O Buffer
Isolated Power and Ground for the output buffers to provide improved noise immunity.
No Connect
Please do not connect. Reserved for future use, i.e. E3: A21, see ballout in Figure 2 on
Page 10.
Data Sheet
11
V2.0, 2003-12-16