HYE18P32161AC Datasheet, PDF (23/33 Pages) Infineon Technologies AG – 32M Asynchronous/Page CellularRAM

HYE18P32161AC(-/L)70/85
32M Asynch/Page CellularRAM
Functional Description
2.5
Asynchronous Write
Writing to the device in asynchronous mode is accomplished by asserting the Chip Select (CS1) and Write Enable
(WE) signals to low. If the Upper Byte (UB) control line is set active low then the upper word (DQ15 to DQ8) of the
data bus is written to the specified memory location. If the Lower Byte (LB) control line is set active low then the
lower word (DQ7 to DQ0) of the data bus is written to the specified memory location. Write operation takes place
when either one or both UB and LB is asserted low. The data is latched by the rising edge of either CS1, WE, or
UB/LB whichever signal comes first.
A20-A0
CS1
UB, LB
WE
DQx IN
DQx OUT
t_AS
Don't Care
t_WC
ADDRESS
t_AW
t_CW
t_BW
t_WP
t_WHZ
t_WR
t_WPH
t_DW
t_DH
Data Valid
t_OW
Figure 12 Asynchronous Write - WE Controlled (OE = V_IH or V_IL, ZZ = V_IH)
A20-A0
CS1
UB, LB
t_WC
ADDRESS
t_AW
t_CW
t_AS
t_BW
t_WR
t_CPH
WE
DQx IN
DQx OUT
Don't Care
t_WP
t_WHZ
t_DW
t_DH
Data Valid
Figure 13 Asynchronous Write - CS1 Controlled (OE = V_IH or V_IL, ZZ = V_IH)
Data Sheet
23
V2.0, 2003-12-16