HYE18P32161AC Datasheet, PDF (32/33 Pages) Infineon Technologies AG – 32M Asynchronous/Page CellularRAM

HYE18P32161AC(-/L)70/85
32M Asynch/Page CellularRAM
Appendix B: S/W Register Entry Mode (“4-cycle method”)
D15
D8 D7 D6 D5 D4 D3 D2 D1 D0 _DQ<15:0>
0
0 PM TCSR DPD* 0
PASR
Control Register
Page Mode Bit
D7
page mode
0 disabled (def.)
1
enabled
Deep Power Down Mode
D4
power down
X disabled (def.)
D15....D8, D3:
reserved, must be set to '0'.
Temperature-Compensated
Self-Refresh
D6 D5 max. case temp.
11
+85°C (def.)
00
+70°C
01
+45°C
10
+15°C
Partial Array Self Refresh
D2 D1 D0 refreshed memory area
0 0 0 entire memory array (def.)
0 0 1 lower 1/2 of memory array
0 1 0 lower 1/4 of memory array
0 1 1 lower 1/8 of memory array
1 0 0 zero
1 0 1 upper 1/2 of memory array
1 1 0 upper 1/4 of memory array
1 1 1 upper 1/8 of memory array
Figure 21 RCR Mapping in S/W Register Entry
Data Sheet
32
V2.0, 2003-12-16