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TC1197 Datasheet, PDF (8/183 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller | |||
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TC1197
Summary of Features
1
Summary of Features
⢠High-performance 32-bit super-scalar TriCore V1.3.1 CPU with 4-stage pipeline
â Superior real-time performance
â Strong bit handling
â Fully integrated DSP capabilities
â Single precision Floating Point Unit (FPU)
â 180 MHz operation at full temperature range
⢠32-bit Peripheral Control Processor with single cycle instruction (PCP2)
â 16 Kbyte Parameter Memory (PRAM)
â 32 Kbyte Code Memory (CMEM)
â 180 MHz operation at full temperature range
⢠Multiple on-chip memories
â 4 or 21) Mbyte Program Flash Memory (PFLASH) with ECC
â 64 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation
â 128 Kbyte Data Memory (LDRAM)
â 40 Kbyte Code Scratchpad Memory (SPRAM)
â Instruction Cache: up to 16 Kbyte (ICACHE, configurable)
â Data Cache: up to 4 Kbyte (DCACHE, configurable)
â 8 Kbyte Overlay Memory (OVRAM)
â 16 Kbyte BootROM (BROM)
⢠16-Channel DMA Controller
⢠32-bit External Bus Interface Unit (EBU) with
â 32-bit demultiplexed / 16-bit multiplexed external bus interface (3.3V, 2.5V)
â Support for Burst Flash memory devices
â Scalable external bus timing up to 75 MHz
⢠Sophisticated interrupt system with 2 à 255 hardware priority arbitration levels
serviced by CPU or PCP2
⢠High performing on-chip bus structure
â 64-bit Local Memory Buses between CPU, EBU, Flash and Data Memory
â 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units
â One bus bridges (LFI Bridge)
⢠Versatile On-chip Peripheral Units
â Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator,
parity, framing and overrun error detection
â Two High-Speed Synchronous Serial Channels (SSC) with programmable data
length and shift direction
â Two serial Micro Second Bus interface (MSC) for serial port expansion to external
power devices
1) Derivative dependent.
Data Sheet
4
V1.1, 2009-05
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