TC1197 Datasheet, PDF (176/183 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1197
Electrical Parameters
5.3.10.2 Micro Second Channel (MSC) Interface Timing
Table 29
Parameter
MSC Interface Timing (Operating Conditions apply), C_L = 50 pF
Symbol
Values
Unit Note /
Min.
Typ. Max.
Test Con
dition
FCLP clock period¹⁾²⁾
SOP/ENx outputs delay
from FCLP rising edge
t₄₀ CC 2 × T_MSC3) –
t₄₅ CC -10
–
ns –
10
ns –
SDI bit time
t₄₆ CC 8 × T_MSC
–
ns –
SDI rise time
t₄₈ SR
100 ns –
SDI fall time
t₄₉ SR
100 ns –
1) FCLP signal rise/fall times are the same as the A2 Pads rise/fall times.
2) FCLP signal high and low can be minimum 1 × T_MSC.
3) T_MSCmin = T_SYS = 1 / f_SYS. When f_SYS = 90 MHz, t₄₀ = 22,2ns
FCLP
SOP
EN
SDI
t₄₀
t₄₅
t₄₅
t₄₈
t₄₆
t₄₆
0.9 V_DDP
0.1 V_DDP
t₄₉
0.9 V_DDP
0.1 V_DDP
MSC_Tmg_1.vsd
Figure 40 MSC Interface Timing
Note: The data at SOP should be sampled with the falling edge of FCLP in the target
device.
Data Sheet
172
V1.1, 2009-05