TC1197 Datasheet, PDF (171/183 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1197
Electrical Parameters
5) If the clock feedback is not enabled, the input signals are latched using the internal clock in the same way as
at asynchronous access. So t5, t6, t7 and t8 from the asynchronous timings apply.
BFCLKI ₁₎
BFCLKO
A[23:0]
Address
Phase(s)
t₁₀
Command
Phase(s)
Burst
Phase(s)
Burst
Phase(s)
Burst Start Address
t₂₂
t₂₂
ADV
Recovery Next Addr.
Phase(s) Phase(s)
t₁₀
Next
Addr.
t₂₂
t₂₁
CS[3:0]
CSCOMB
RD
RD/WR
BAA
t₁₂
t_22a
t₂₁
t₂₁
t₁₂
t_22a
D[31:0]
(32-Bit)
t₂₄
t₂₃
Data (Addr+0)
t₂₄
t₂₃
Data (Addr+4)
D[15:0]
(16-Bit)
WAIT
t₂₆
t₂₅
Data (Addr+0) Data (Addr+2)
1) _{Output delays are always referenced to BCLKO. The reference clock for input}
characteristics depends on bit EBU_BFCON.FDBKEN.
EBU_BFCON.FDBKEN = 0: BFCLKO is the input reference clock.
EBU_BFCON.FDBKEN = 1: BFCLKI is the input reference clock (EBU clock
feedback enabled).
BurstRDWR_4.vsd
Figure 37 EBU Burst Mode Read / Write Access Timing
Data Sheet
167
V1.1, 2009-05