TC1197 Datasheet, PDF (31/183 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1197
Introduction
In TC1197 the PMU1 contains 2 Mbyte of Program Flash realized as one Flash bank. It
does not contain any Data Flash.
Since in TC1197 the two PMUs can work in parallel, further combinations of concurrent
operations are supported if those are operating on Flash modules in different PMUs, e.g.
• Read data from Flash1 while accessing code from Flash0.
• Read code or data from one Flash while the other Flash is busy with program or erase
operation.
• Both Flash modules are concurrently busy with program or erase operation.
Both, the Program Flash and the Data Flash, provide error correction of single-bit errors
within a 64-bit read double-word, resulting in an extremely low failure rate. Read
accesses to Program Flash are executed in 256-bit width, to Data Flash in 64-bit width
(both plus ECC). Single-cycle burst transfers of up to 4 double-words and sequential
prefetching with control of prefetch hit are supported for Program Flash.
The minimum programming width is the page, including 256 bytes in Program Flash and
128 bytes in Data Flash. Concurrent programming and erasing in Data Flash is
performed using an automatic erase suspend and resume function.
A basic block diagram of the Flash Module is shown in the following figure.
Control
Addr Bus
64
Write Bus
64
Read Bus
Flash Command
State Machine FCS
ECC Block
Control
Address
64
WR_DATA
8
ECC Code
8
64
RD_DATA
FSI
SFRs
FSRAM
Microcode
Redundancy
Control
Voltage Control
Page
Write
Buffers
256 byte
and
128 byte
Program
Flash
PF-Read
Buffer
256+32 bit
and
DF-Read
Buffer
64+8 bit
Bank 0
Data
Flash
Bank 1
Bank 0
Bank 1
Flash Interface&Control Module
FIM
PMU
Flash Array Module
FAM
Flash FSI & Array
Figure 4
Basic Block Diagram of Flash Module
Flash_BasicBlockDiagram_generic.vsd
All Flash operations are controlled simply by transferring command sequences to the
Flash which are based on JEDEC standard. This user interface of the embedded Flash
is very comfortable, because all operations are controlled with high level commands,
such as “Erase Sector”. State transitions, such as termination of command execution, or
errors are reported to the user by maskable interrupts. Command sequences are
Data Sheet
27
V1.1, 2009-05