TC1197 Datasheet, PDF (47/183 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

Figure 10 shows a general block diagram of the MLI module.
TC1197
Introduction
f_SYS
TR[3:0]
BRKOUT
SR[7:0]
Fract.
Divider
MLI
Transmitter
I/O
Control
f_MLI
MLI Module
Move
Engine
MLI
Receiver
I/O
Control
TREADY[D:A] ₄
TVALID[D:A] ₄
TDATA
TCLK
RCLK[D:A] 4
RREADY[D:A] ₄
RVALID[D:A] ₄
RDATA[D:A] 4
Port
Control
MCB06062_mod
Figure 10 General Block Diagram of the MLI Modules
The MLI transmitter and MLI receiver communicate with other MLI receivers and MLI
transmitters via a four-line serial connection each. Several I/O lines of these connections
are available outside the MLI module kernel as a four-line output or input vector with
index numbering A, B, C and D. The MLI module internal I/O control blocks define which
signal of a vector is actually taken into account and also allow polarity inversions (to
adapt to different physical interconnection means)
Data Sheet
43
V1.1, 2009-05