TC1197 Datasheet, PDF (174/183 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1197
Electrical Parameters
Note: The generation of RREADYx is in the input clock domain of the receiver. The
reception of TREADYx is asynchronous to TCLKx.
Table 28
Parameter
MLI Timings (Operating Conditions apply), C_L = 50 pF
Symbol
Values
Min.
Typ. Max.
Unit Note /
Test Co
ndition
MLI Transmitter Timing
TCLK clock period
TCLK high time
TCLK low time
TCLK rise time
TCLK fall time
TDATA/TVALID output
delay time
t₁₀ CC 2 × T_MLI –
–
ns ¹⁾
t_{11 CC} 0.45 × t₁₀ 0.5 × t₁₀ 0.55 × t₁₀ ns ²⁾³⁾
t₁₂ CC 0.45 × t₁₀ 0.5 × t₁₀ 0.55 × t₁₀ ns ²⁾³⁾
t₁₃ CC –
–
4)
ns –
t₁₄ CC –
–
4)
ns –
t₁₅ CC -3
–
4.4
ns –
TREADY setup time to
t₁₆ SR 18
–
–
TCLK rising edge
ns –
TREADY hold time from t₁₇ SR 0
TCLK rising edge
–
–
ns –
MLI Receiver Timing
RCLK clock period
RCLK high time
RCLK low time
t₂₀ SR 1 × T_MLI –
–
t₂₁ SR –
0.5 × t₂₀ –
t₂₂ SR –
0.5 × t2 –
0
ns ¹⁾
ns ⁵⁾⁶⁾
ns ⁵⁾⁶⁾
RCLK rise time
t23 S –
R
–
4
ns ⁷⁾
RCLK fall time
t24 S –
R
–
4
ns ⁷⁾
RDATA/RVALID setup t25 S 4.2
–
–
time to RCLK falling edge R
ns –
RDATA/RVALID hold time t26 S 2.2
–
–
from RCLK rising edge R
ns –
RREADY output delay time t27 C 0
C
–
16
ns –
1) T_MLImin. = T_SYS = 1/f_SYS. When f_SYS = 90 MHz, t₁₀ = 22.22 ns and t₂₀ = 11.11 ns.
2) The following formula is valid: t₁₁ + t₁₂ = t₁₀
Data Sheet
170
V1.1, 2009-05