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TC1197 Datasheet, PDF (28/183 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller | |||
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TC1197
Introduction
⢠The Boot ROM interface.
⢠The Emulation Memory interface.
⢠The Local Memory Bus LMB slave interface.
Following memories are controlled by and belong to the PMU0:
⢠2 Mbyte of Program Flash memory (PFlash)
⢠64 Kbyte of Data Flash memory (DFlash, represents 16 Kbyte EEPROM)
⢠16 Kbyte of Boot ROM (BROM)
⢠8 Kbyte Overlay RAM (OVRAM)
In the TC1197 an additional PMU is included with only a subset of PMU0âs submodules:
⢠The Flash command and fetch control interface but only for Program Flash.
⢠The Local Memory Bus LMB slave interface.
The following memories are controlled and belong to the PMU1:
⢠2 Mbyte of Program Flash memory (PFlash).
Because of its independence from PMU0 this second PMU enables additional
functionality: Read while Write (RWW), Write while Write (WWW) or concurrent data and
instruction accesses, if those are operating on different PMUs.
Data Sheet
24
V1.1, 2009-05
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