TC1197 Datasheet, PDF (58/183 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1197
Introduction
2.6.1 On-Chip Debug Support
The classic software debug approach (start/stop, single-stepping) is supported by
several features labelled “OCDS Level 1”:
• Run/stop and single-step execution independently for TriCore and PCP.
• Means to request all kinds of reset without usage of sideband pins.
• Halt-after-Reset for repeatable debug sessions.
• Different Boot modes to use application software not yet programmed to the Flash.
• A total of four hardware breakpoints for the TriCore based on instruction address,
data address or combination of both.
• Unlimited number of software breakpoints (DEBUG instruction) for TriCore and PCP.
• Debug event generated by access to a specific address via the system bus.
• Tool access to all SFRs and internal memories independent of the Cores.
• Two central Break Switches to collect debug events from all modules (TriCore, PCP,
DMA, BCU, break input pins) and distribute them selectively to breakable modules
(TriCore, PCP, break output pins).
• Central Suspend Switch to suspend parts of the system (TriCore, PCP, Peripherals)
instead if breaking them as reaction to a debug event.
• Dedicated interrupt resources to handle debug events inside TriCore (breakpoint
trap, software interrupt) and Cerberus (can trigger PCP), e.g. for implementing
Monitor programs.
• Access to all OCDS Level 1 resources also for TriCore and PCP themselves for
debug tools integrated into the application code.
• Triggered Transfer of data in response to a debug event; if target is programmed to
be a device interface simple variable tracing can be done.
• In depth performance analysis and profiling support given by the Emulation Device
through MCDS Event Counters driven by a variety of trigger signals (e.g. cache hit,
wait state, interrupt accepted).
2.6.2 Real Time Trace
For detailed tracing of the system’s behavior a pin-compatible Emulation Device will be
available.¹⁾
2.6.3 Calibration Support
Two main use cases are catered for by resources in addition the OCDS Level 1
infrastructure: Overlay of non-volatile on-chip memory and non-intrusive signaling:
• 8 KB SRAM for Overlay.
• Can be split into up to 16 blocks which can overlay independent regions of on-chip
Data Flash.
1) The OCDS L2 interface of AudoNG is not available.
Data Sheet
54
V1.1, 2009-05