TC1197 Datasheet, PDF (59/183 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1197
Introduction
• Changing the configuration is triggered by a single SFR access to maintain
consistency.
• Overlay configuration switch does not require the TriCore to be stopped or
suspended.
• Invalidation of the Data Cache (maintaining write-back data) can be done
concurrently with the same SFR.
• 256 KB additional Overlay RAM on Emulation Device.
• The 256 KB Trace memory of the Emulation Device can optionally be used for
Overlay also.
• A dedicated trigger SFR with 32 independent status bits is provided to centrally post
requests from application code to the host computer.
• The host is notified automatically when the trigger SFR is updated by the TriCore or
PCP. No polling via a system bus is required.
2.6.4 Tool Interfaces
Three options exist for the communication channel between Tools (e.g. Debugger,
Calibration Tool) and TC1197:
• Two wire DAP (Device Access Port) protocol for long connections or noisy
environments.
• Four (or five) wire JTAG (IEEE 1149.1) for standardized manufacturing tests.
• CAN (plus software linked into the application code) for low bandwidth deeply
embedded purposes.
• DAP and JTAG are clocked by the tool.
• Bit clock up to 40 MHz for JTAG, up to 80 MHz for DAP.
• Hot attach (i.e. physical disconnect/reconnect of the host connection without reset of
the TC1197) for all interfaces.
• Infineon standard DAS (Device Access Server) implementation for seamless,
transparent tool access over any supported interface.
• Lock mechanism to prevent unauthorized tool access to critical application code.
2.6.5 Self-Test Support
Some manufacturing tests can be invoked by the application (e.g. after power-on) if
needed:
• Hardware-accelerated checksum calculation (e.g. for Flash content).
• RAM tests optimized for the implemented architecture.
2.6.6 FAR Support
To efficiently locate and identify faults after integration of a TC1197 into a system special
functions are available:
• Boundary Scan (IEEE 1149.1) via JTAG and DAP.
Data Sheet
55
V1.1, 2009-05