TC1197 Datasheet, PDF (26/183 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1197
Introduction
2.3.4 System Control Unit
The following SCU introduction gives an overview about the TC1197 System Control
Unit (SCU) For Information about the SCU see chapter 3.
2.3.4.1 Clock Generation Unit
The Clock Generation Unit (CGU) allows a very flexible clock generation for the TC1197.
During user program execution the frequency can be programmed for an optimal ratio
between performance and power consumption.
2.3.4.2 Features of the Watchdog Timer
The main features of the WDT are summarized here.
• 16-bit Watchdog counter
• Selectable input frequency: f_FPI/256 or f_FPI/16384
• 16-bit user-definable reload value for normal Watchdog operation, fixed reload value
for Time-Out and Prewarning Modes
• Incorporation of the ENDINIT bit and monitoring of its modifications
• Sophisticated Password Access mechanism with fixed and user-definable password
fields
• Access Error Detection: Invalid password (during first access) or invalid guard bits
(during second access) trigger the Watchdog reset generation
• Overflow Error Detection: An overflow of the counter triggers the Watchdog reset
generation
• Watchdog function can be disabled; access protection and ENDINIT monitor function
remain enabled
• Double Reset Detection
2.3.4.3 Reset Operation
The following reset request triggers are available:
• 1 External power-on hardware reset request trigger; PORST, (cold reset)
• 2 External System Request reset triggers; ESR0 and ESR1,(warm reset)
• Watchdog Timer (WDT) reset request trigger, (warm reset)
• Software reset (SW), (warm reset)
• Debug (OCDS) reset request trigger, (warm reset)
• Resets via the JTAG interface
There are two basic types of reset request triggers:
• Trigger sources that do not depend on a clock, such as the PORST. This trigger force
the device into an asynchronous reset assertion independently of any clock. The
activation of an asynchronous reset is asynchronous to the system clock, whereas
its de-assertion is synchronized.
Data Sheet
22
V1.1, 2009-05