TC1167 Datasheet, PDF (52/127 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1167
Introduction
2.4.7.2 FADC Short Description
General Features
• Extreme fast conversion, 21 cycles of f_FADC clock (262.5 ns @ f_FADC = 80 MHz)
• 10-bit A/D conversion (higher resolution can be achieved by averaging of
consecutive conversions in digital data reduction filter)
• Successive approximation conversion method
• Each differential input channel can also be used as single-ended input
• Offset calibration support for each channel
• Programmable gain of 1, 2, 4, or 8 for each channel
• Free-running (Channel Timers) or triggered conversion modes
• Trigger and gating control for external signals
• Built-in Channel Timers for internal triggering
• Channel timer request periods independently selectable for each channel
• Selectable, programmable digital anti-aliasing and data reduction filter block with four
independent filter units
Clock
Control
V_FAREF V_DDAF V_DDMF V_DDIF
V_FAGND V_SSAF V_SSMF
f_FADC
f_CLC
Data
Reduction
Unit
Interrupt ^SRx
Control
SRx
DMA
A/D
Control
A/D
Converter
Stage
FAIN0P
FAIN0N
FAIN1P
FAIN1N
FAIN2P
FAIN2N
FAIN3P
FAIN3N
input
channel 0
input
channel 1
input
channel 2
input
channel 3
TS[H:A]
GS[H:A]
Channel
Trigger
Control
Channel
Timers
MCB06065_m4
Figure 13 Block Diagram of the FADC Module with 4 Input Channels
As shown in Figure 13, the main FADC functional blocks are:
• An Input Structure containing the differential inputs and impedance control.
Data Sheet
48
V1.3, 2009-10