TC1167 Datasheet, PDF (37/127 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1167
Introduction
f_SSC
Clock
Control ^f_CLC
Address
Decoder
RIR
Interrupt ^TIR
Control
EIR
DMA Requests
SSC
Module
(Kernel)
Master
MRSTA
MRSTB
MTSR
Slave
MTSRA
MTSRB
MRST
Slave
Master
Slave
Master
SCLKA
SCLKB
SCLK
SLSI[7:1]
SLSO[7:0]
SLSOANDO[7:0]
SLSOANDI[7:0]
Enable
M/S Select
Port
Control
MTSR
MRST
SCLK
SLSI[7:1]
SLSO[7:0]
SLSOANDO[7:0]
MCB06058_mod
Figure 6 General Block Diagram of the SSC Interface
The SSC supports full-duplex and half-duplex serial synchronous communication up to
40 Mbit/s (@ 80 MHz module clock, Master Mode). The serial clock signal can be
generated by the SSC itself (Master Mode) or can be received from an external master
(Slave Mode). Data width, shift direction, clock polarity and phase are programmable.
This allows communication with SPI-compatible devices. Transmission and reception of
data are double-buffered. A shift clock generator provides the SSC with a separate serial
clock signal. One slave select input is available for slave mode operation. Eight
programmable slave select outputs (chip selects) are supported in Master Mode.
Data Sheet
33
V1.3, 2009-10