TC1167 Datasheet, PDF (120/127 Pages) Infineon Technologies AG – 32-Bit Single-Chip Microcontroller

TC1167
Electrical Parameters
7) The RCLK max. input rise/fall times are best case parameters for f_SYS = 80 MHz. For reduction of EMI, slower
input signal rise/fall times can be used for longer RCLK clock periods.
5.3.8.2 Micro Second Channel (MSC) Interface Timing
Table 23
Parameter
MSC Interface Timing (Operating Conditions apply), C_L = 50 pF
Symbol
Values
Unit Note /
Min.
Typ. Max.
Test Con
dition
FCLP clock period¹⁾²⁾
SOP/ENx outputs delay
from FCLP rising edge
t₄₀ CC 2 × T_MSC3) –
t₄₅ CC -10
–
ns –
10
ns –
SDI bit time
t₄₆ CC 8 × T_MSC
–
ns –
SDI rise time
t₄₈ SR
100 ns –
SDI fall time
t₄₉ SR
100 ns –
1) FCLP signal rise/fall times are the same as the A2 Pads rise/fall times.
2) FCLP signal high and low can be minimum 1 × T_MSC.
3) T_MSCmin = T_SYS = 1/f_SYS. When f_SYS = 80 MHz, t₄₀ = 25 ns
t₄₀
FCLP
t₄₅
t₄₅
SOP
EN
0.9 V_DDP
0.1 V_DDP
t₄₈
t₄₉
SDI
0.9 V_DDP
0.1 V_DDP
t₄₆
t₄₆
MSC_Tmg_1.vsd
Figure 33 MSC Interface Timing
Note: Sample the data at SOP with the falling edge of FCLP in the target device.
Data Sheet
115
V1.3, 2009-10